1. Field of Invention
The present invention relates to a method of forming an integrated circuit, and more generally to a method of forming a semiconductor device.
2. Description of Related Art
In the field of integrated circuit devices, the dimensions of devices are often reduced to attain a higher operating speed and a lower power consumption. However, with the ever-increasing level of integration of devices, the miniaturization of devices has almost reached its limit. Strain engineering is one of the promising approaches to circumvent the scaling limit.
A method for strain control is utilizing materials having an identical crystal structure but different lattice constants to achieve the purpose of controlling the strain. If a transistor is an N-type transistor, implanted strain atoms are carbon atoms and formed into an epitaxial structure of silicon carbide (SiC). Since the lattice constant of carbon atoms is usually smaller than that of silicon atoms, if SiC is embedded in source and drain regions, a tensile stress can be generated in the channel to enhance the mobility of electrons so that the driving current of the device is increased. If a transistor is a P-type transistor, implanted strain atoms are germanium atoms and formed into an epitaxial structure of silicon germanium (SiGe). A compression stress can be generated in the channel to enhance the mobility of holes.
Therefore, controlling the strain in the channel region of a transistor is indeed a proposed solution to overcome the limitation imposed by the device miniaturization. However, it has been challenging to integrate the strain engineering into the existing CMOS process.